Modern semiconductor design relies heavily on the use of various software tools, which perform the tasks required to implement a desired circuit design onto silicon. In general, a traditional serial design process, as shown in FIG. 1 element 100, begins with a definitional design 102 which, as it names implies, describes the desired logical, timing and power parameters of the desired circuit. The definitional design is typically implemented in a computer readable file written in a hardware description language (“HDL”) such as Verilog, HDL, VHDL, DSL, etc. The definitional design is also referred to as a behavioral description or model of the circuit. The HDL file is then provided to two categories of tools, which are used to test the design and convert the HDL into other computer readable files needed to actually fabricate the circuit.
The first category includes functional design and verification tools 104 (e.g., simulation tools) which are used to test the circuit's logical performance (i.e., whether the circuit generates the desired output signals in response to a predefined set of input signals). The functional design and verification tools are typically software implemented processes which are run on a workstation or other computer processors. These tools use the HDL file to create a software model of the definitional design. A variety of simulated inputs may then be applied to the software model. The resulting outputs of the model are recorded and compared to expected outputs to determine whether the definitional design produced the logical results required. Since simulation is concerned, primarily, with the logical performance of the design, simulation tools are largely technology independent (i.e., the design has not been mapped to specific cell libraries which contain data for constructing actual electronic components according to known fabrication processes).
The second category includes synthesis and implementation tools. Like simulation tools, synthesis and implementation tools are typically implemented in software which runs on a workstation or other computer processor. However, these tools are highly technology dependent and are used to create an implementation of the circuit components onto the chip. Specifically, logic synthesis tools 106 are used to generate a mapped logic “netlist”, which contains a description of the gates and interconnections between gates for the desired circuit. Within traditional logic synthesis tool 106, interconnect delay is modeled using wire-load models (WLM's). Wire load models are statistical predictors of average net behavior which predict wire capacitance, not length or resistance. A designer iterates between synthesis, HDL changes and choice of WLM's (with the aid of a floorplanning tool 108) until synthesis indicates timing closure at the proposed area.
Recently, synthesis tool vendors have added power optimization (i.e., minimization of power consumption), to this logic optimization process. Once the designer achieves closure in synthesis, Design for Testability logic 110 is inserted into the design. This logic includes scan chains, and more powerful DFT extensions such as IEEE 1149.1 structures and Logic Built-in Self Test. The designer defines and inserts clock (and other fanout) powering networks. Next, sign-off tools 112, such as timing analysis, are applied to the design, to assess conformance to criteria for entry into the layout process.
The design then enters the layout process. First, a netlist is provided to a placement tool 114. The placement tool 114 determines where the gates of the circuit will be physically located within a location on the chip which has been predesignated to contain the circuit. This location is referred to as the “image”. Physical designers measure timing based on estimated wire delays using methods such as Steiner estimation. The physical designers also resolve timing and congestion problems, using a variety of optimization tools 118 and manual changes, until estimated timing and congestion appear to be good. Sometimes, these problems require logic or floorplan changes by the logic designer, requiring a design handoff between the logic design and the physical designer. Then, further optimization tools are used to re-order the scan chains to minimize wire lengths and latch wire loads. The designer balances the clocks using a clock optimization tool, which re-organizes the connectivity amongst clock buffers and latches with respect to placement, and minimizes buffer loading towards an objective of minimal clock skew at each level of repowering.
After the circuit has been placed, the data from the placement tools is provided to a router 116. The router generates the fabrication data required to construct the metal lines on the chip that connect the components of the circuit together. After routing, parasitics for final timing analysis are extracted. At this point, further engineering changes (ECO's) may be required to fix timing issues such as early mode hold problems, or to alleviate congestion issues. Again, this may require a design hand-off between the physical designer and the logic designer. These final fixes are affected using various optimization tools 118 and manual means. Prior to release of the design to manufacturing, a test engineer produces a set of test vectors for the design, where a final set of manufacturability checks are executed.
After routing and verification, all the files containing the computer data required to fabricate an implementation of the circuit are available. This is referred to as the final design data 120. The final design data is then sent to manufacturing where the final design data from other circuits on the chip are integrated together and the actual chip is manufactured.
In the traditional design flow of FIG. 1, there is significant iteration between design engineering actions (in both the logical and physical design disciplines) and the CPU-intensive tasks of logical & physical design processing and logical and physical optimization.
Recent advances in the area of Placement Driven Synthesis (PDS) have improved this situation. As shown in FIG. 2 element 200, placement driven synthesis techniques can be executed as an early timing closure technique, in which an enhanced logical synthesis tool 202 creates an initial placement that is simultaneously optimized with the logic design. In other words, PDS optimizes a design for timing and area based on input constraints (e.g., timing constraints, die size, technology information, etc.). PDS requires some initial block-level floorplanning, as provided by floorplanner 204. A timing closure feedback loop exists whereby information from logic synthesis 202 is passed back through a timing correction tool 206 and block level floorplanner 204, before being fed back into the logic synthesis tool 202. Since placement information is available within PDS, actual wirelengths, rather than WLM's, are available to aid the designer when optimizing the logic design.
After this early timing closure, the logic designer proceeds to DFT logic and clock logic insertion 110. Placement Driven Synthesis techniques can also be executed as a late timing closure technique by the physical designer. A fully placed design, with an estimated, global, or detailed route, is optimized using a placement-based synthesis tool 208 capable of localized changes to the logic and/or the placement, to fix localized timing or electrical issues. Thus, Placement Driven Synthesis improves the total design process flow by reducing the number of design iterations required between the physical and logical design engineers.
The Placement Driven Synthesis operation is a very complex, multi-step, compute-intensive process which can take several days to complete. Existing design automation tools can be used to graphically view congestion information related to the design before or after PDS optimization. However, executing a post-PDS process step can be time consuming and is meant mostly for interactive debug. In addition, such a step only provides a snapshot of what a design looks like at the end of PDS, and not during the process.
There is a need for a tool to provide graphical congestion data concurrent with a placement driven synthesis operation. Such a tool should provide a graphical, real-time snapshot of what the design looks like during several steps within the placement driven synthesis process. Such information would enable a design engineer to make changes and/or improvements to subsequent processes in the design flow before the current placement driven synthesis step completes, thus saving time. This information would also provide valuable debug information to PDS developers.